At present, flash memory is widely used as a non-volatile semiconductor memory device, but with the aim of replacing flash memory, there is progress in the development of various types of semiconductor memory device. These include resistance variable memory cells, where resistance variable elements are used to store information of logic 0 and logic 1 according to resistance value. A representative variable resistance element may be an STT-RAM (Spin Transfer Torque-Random Access Memory) that performs spin injection magnetization reversal writing using a magnetic tunnel junction (MTJ) element, or a Re-RAM (Resistive-Random Access Memory) that uses a metal oxide or the like.
In order to perform sense-amplification of signals read from these resistance variable memory cells, a method using reference cells is generally employed. A reference cell method may be a method of generating a reference signal (reference voltage or reference current) using a memory cell that has an intermediate resistance value between two resistance values respectively corresponding to logic 0 and logic 1, or a method of using two memory cells having resistance values corresponding respectively to logic 0 and logic 1, and generating a reference signal equivalent to an intermediate resistance value thereof.
JP Patent Kokai Publication No. 2009-211742A (Patent Literature 1) discloses an error correction device and an error correction method which, in a case of error exceeding data error correction capability in data that is read from a non-volatile memory, can prevent the addition of further error.
JP Patent Kokai Publication No. 2006-244541A (Patent Literature 2) discloses a semiconductor memory device provided with an error correction circuit that uses ECC (Error Correction Code) corresponding to a sense amplifier of a DRAM. In the semiconductor memory device, when there is an error in sense-amplified data at a stage when a page is open, the error is corrected. Check bit information is then generated at a stage when the page is closed, and rewriting thereof is performed along with data bits.
The following analysis is given from a viewpoint of the present invention.
In a case of using a reference cell method in a semiconductor memory device, in order to reduce a size of the device and save cost, the number of reference cells may be reduced, and one reference cell may be shared by a plurality of sense amplifiers. In such a case, if an error exists in a reference cell, a plurality of data amplified based on the reference cell will have errors too. These errors are problems for a semiconductor device adopting the reference cell.